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ds07-12526-1e fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89920 series mb89923/925/p928/pv920 n description the mb89920 series is a line of single-chip microcontrollers using the f 2 mc*-8l cpu core which can operate at low voltage but at high speed. the microcontrollers in this series contain peripheral functions such as a pwm timer, an input capture/output compare control counter, an lcd controller/driver, an a/d converter, and a uart. the mb89920 series can suit a wide range of applications such as analog input conversion, pulse input measurement/pulse output control, serial communications control, and display control. *: f 2 mc stands for fujitsu flexible microcontroller. n features ? high speed processing at low voltage minimum execution time: 0.5 m s/8.0 mhz ?f 2 mc-8l family cpu core ? 8-bit pwm timer: 2 channels (also usable as a reload timer) ? 16-bit input capture: 2 channels / 16-bit output compare: 2 channels (continued) n package multiplication and division instructions 16-bit arithmetic operations test and branch instructions bit manipulation instructions, etc. instruction set optimized for controllers (mqp-80c-p01) (fpt-80p-m06) 80-pin plastic qfp 80-pin ceramic mqfp
2 mb89920 series (continued) ? 20-bit time-base counter ? uart: 1 channel (with asynchronous transfer mode and 8-bit synchronous serial mode) ? 8-bit serial interface: 1 channel (lsb first/msb first selectability) ? 10-bit a/d converter: 8 channels ? lcd controller/driver: 28 segments 4 commons (max. 112 pixels) ? low-voltage detection reset ? watchdog timer reset ? external interrupt: 4 channels four channels are independent and capable of wake-up from the low-power consumption mode (with edge detection function) ? buzzer output/clock output ? low-power consumption modes: stop mode (the software stops oscillation to minimize the current consumption.) sleep mode (the cpu stops to reduce current consumption to approx. 1/3 of normal.) hardware standby mode (the pin input stops oscillation.)
3 mb89920 series n product lineup * : the minimum operating voltage varies with conditions such as the operating frequencies, functions, and development tool. mb89925 mb89p928 mb89pv920 classification mass production products (mask rom products) one-time prom product (for development) piggyback/evaluation product (for development) rom size 8 k 8 bits (internal mask rom) 16 k 8 bits (internal mask rom) 48 k 8 bits (internal prom) 48 k 8 bits (external rom) ram size 256 8 bits 512 8 bits 1024 8 bits cpu functions number of instructions: 136 instruction bit length: 8 bits instruction length: 1 to 3 bytes data bit length: 1, 8, 16 bits minimum execution time: 0.5 m s/8 mhz interrupt processing time: 4.5 m s/8 mhz ports i/o ports (cmos): 35 (25 ports also serve as peripherals.) i/o ports (n-ch open-drain): 34 (all also serve as peripherals.) to t a l : 6 9 options specify with mask options set with eprom programmer none 20-bit time-base timer 20 bits (interval time selection: 4.10 ms, 16.38 ms, 65.54 ms, 262 ms/8 mhz) real-time i/o 16-bit timer: operating clock cycle (0.5 m s, 1.0 m s, 2.0 m s, 4.0 m s), overflow interrupt input capture: 16 bits 2 channels, external trigger edge selectability output compare: 16 bits 2 channels lcd controller/ driver common output: 4 (selectable from 2 to 4 by software) segment output: 28 (can be switched to ports in 4-pin unit by software) bias power supply pins: 3 lcd display ram size: 14 8 bits dividing resistor for lcd driving: bult-in (external resistor selectability) 8-bit pwm timer 8 bits 2-channel reload timer operation 8 bits 2-channel pwm operation (4 cycles selectable) 8 bits 1-channel ppg operation (4 oscillation clocks selectable) uart variable data length (7 or 8 bits), internal baud rate generator, error detection function, full-duplex with internal double buffer, nrz transmission formation, clock synchronous/asynchronous transfer capable 8-bit serial i/o 8 bits, lsb first/msb first selectability, one clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 1.0 m s, 4.0 m s, 16.0 m s) 10-bit a/d converter 10-bit resolution 8 channels a/d conversion mode (conversion time: 16.5 m s (33 instruction cycles)) sense mode (conversion time: 9.0 m s (18 instruction cycles)) continuous activation by an internal clock capable watchdog timer interval time: approx. 130 to 260 ms low-voltage detection reset reset activation voltage: 3.0 to 4.3 v reset release voltage: 3.1 to 4.5 v hardware standby stop the clock oscillation by pin input buzzer/clock output 1 channel (output a frequency from 1 khz, 2 khz, 4 khz, and divided clock frequency) external interrupt 4 channels (rising edge/falling edge selectability) package qfp-80 mqfp-80 operating voltage 2.2 to 6.0 v* 2.7 to 6.0 v* 2.7 to 6.0 v* eprom for use ? mbm27c512-20tv (lcc package) mb89923 part number parameter
4 mb89920 series n package and corresponding products : available : not available note: for more information about each package, see section n package dimensions. n differences among products 1. memory size before evaluating using the piggyback product, verify its differences from the product that will actually be used. take particular care on the following points: ? the stack area, etc., is set at the upper limit of the ram. ? the external area is used. 2. current consumption ? in the case of the mb89pv920, add the current consumed by the eprom which is connected to the top socket. ? when operated at low speed, the product with an otprom (one-time prom) or an eprom will consume more current than the product with a mask rom. however, the current consumption in sleep/stop modes is the same. (for more information, see section n electrical characteristics.) 3. mask options functions that can be selected as options and how to designate these options vary by the product. before using options check section n mask options. package mb89923 mb89925 mb89p928 mb89pv920 fpt-80p-m06 mqp-80c-p01
5 mb89920 series n pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p72/seg18 p73/seg19 p74/seg20 p75/seg21 p76/seg22 p77/seg23 p80/seg24 p81/seg25 p82/seg26 p83/seg27 p90/rto0 p91/rto1 p92/clk p93/pwm0 v ss moda x1 x0 p94/pwm1 hst rst p95/sck p96/so p97/si 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p51/seg1 p50/seg0 p40/com0 p41/com1 p42/com2 p43/com3 p44/v1 p45/v2 v3 v cc av cc avr av ss p10/an0 p11/an1 p12/an2 p13/an3 p14/an4 p15/an5 p16/an6 p17/an7 p00/int0 p01/int1 p02/int2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 p71/seg17 p70/seg16 p67/seg15 p66/seg14 p65/seg13 p64/seg12 p63/seg11 p62/seg10 p61/seg9 p60/seg8 p57/seg7 p56/seg6 p55/seg5 p54/seg4 p53/seg3 p52/seg2 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p32/uck p31/uo p30/ui p27 p26 p25 p24 p23/rti1 p22 p21 p20/rti0 p07 p06 p05 p04 p03/int3 (top view) (fpt-80p-m06) (lead pitch: 0.80 mm) (body size: 20 mm 14 mm) (only for mass production or one-time prom products)
6 mb89920 series ? pin assignment on package top (only for piggyback/evaluation product) n.c.: internally connected. do not use. (only for piggyback/evaluation product) pin no. pin name pin no. pin name pin no. pin name pin no. pin name 81 n.c. 89 ad2 97 n.c. 105 oe /v pp 82 a15 90 ad1 98 o4 106 n.c. 83 a12 91 ad0 99 o5 107 a11 84 ad7 92 n.c. 100 o6 108 a9 85 ad6 93 o1 101 o7 109 a8 86 ad5 94 o2 102 o8 110 a13 87 ad4 95 o3 103 ce 111 a14 88 ad3 96 v ss 104 a10 112 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p72/seg18 p73/seg19 p74/seg20 p75/seg21 p76/seg22 p77/seg23 p80/seg24 p81/seg25 p82/seg26 p83/seg27 p90/rto0 p91/rto1 p92/clk p93/pwm0 v ss moda x1 x0 p94/pwm1 hst rst p95/sck p96/so p97/si 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p51/seg1 p50/seg0 p40/com0 p41/com1 p42/com2 p43/com3 p44/v1 p45/v2 v3 v cc av cc avr av ss p10/an0 p11/an1 p12/an2 p13/an3 p14/an4 p15/an5 p16/an6 p17/an7 p00/int0 p01/int1 p02/int2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 p71/seg17 p70/seg16 p67/seg15 p66/seg14 p65/seg13 p64/seg12 p63/seg11 p62/seg10 p61/seg9 p60/seg8 p57/seg7 p56/seg6 p55/seg5 p54/seg4 p53/seg3 p52/seg2 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p32/uck p31/uo p30/ui p27 p26 p25 p24 p23/rti1 p22 p21 p20/rti0 p07 p06 p05 p04 p03/int3 101 102 103 104 105 106 107 108 109 93 92 91 90 89 88 87 86 85 100 99 98 97 96 95 94 110 111 112 81 82 83 84 (top view) (mqp-80c-p01)
7 mb89920 series n pin description (continued) pin no. pin name circuit type function 17 x1 a clock oscillator pins 18 x0 16 moda b operation mode selection input pin connect this pin to v ss (gnd). 20 hst b hardware standby input pin 21 rst c reset i/o pin this pin is an n-ch open-drain output type with a pull-up resistor, and a hysteresis input type. l is output from this pin by an internal reset source. the internal circuit is initialized by the input of l. 11, 12 p90/rto0, p91/rto1 d general-purpose i/o ports a pull-up resistor option is provided. also serve as an output compare data output. 13 p92/buz/clk d general-purpose i/o port also serves as a buzzer/clock output. 14 p93/pwm0 d general-purpose i/o port a pull-up resistor option is provided. also serves as an 8-bit pwm output. 19 p94/pwm1 d general-purpose i/o port a pull-up resistor option is provided. also serves as an 8-bit pwm output. 22 p95/sck e general-purpose i/o port a pull-up resistor option is provided. also serves as the clock i/o (sck) for the serial i/o. the sck input is a hysteresis input. the output type can be switched between n-ch open-drain and cmos. 23 p96/so d general-purpose i/o port a pull-up resistor option is provided. also serves as the data output (so) for the serial i/o. the output type can be switched between n-ch open-drain and cmos. 24 p97/si e general-purpose i/o port a pull-up resistor option is provided. also serves as the data input (si) for the serial i/o. 25 p32/uck e general-purpose i/o port a pull-up resistor option is provided. also serves as a uart clock i/o (uck). the uck input is hysteresis input. the output type can be switched between n-ch open-drain and cmos. 26 p31/uo d general-purpose i/o port a pull-up resistor option is provided. also serves as a uart data output (uo). the output type can be switched between n-ch open-drain and cmos.
8 mb89920 series (continued) pin no. pin name circuit type function 27 p30/ui e general-purpose i/o port a pull-up resistor option is provided. also serves as a uart data input (ui). 28 to 31 p27 to p24 d general-purpose i/o ports a pull-up resistor option is provided. 32 p23/rti1 e general-purpose i/o port a pull-up resistor option is provided. also serves as an input capture data input. 33, 34 p22, p21 d general-purpose i/o ports a pull-up resistor option is provided. 35 p20/rti0 e general-purpose i/o port a pull-up resistor option is provided. also serves as an input capture data input. 36 to 39 p07 to p04 d general-purpose i/o ports a pull-up resistor options is provided. 40 to 43 p03/int3 to p00/int0 e general-purpose i/o ports a pull-up resistor options is provided. also serve as an external interrupt input (int0 to int3). 44 to 51 p17/an7 to p10/an0 g cmos i/o ports also serve as an a/d converter analog input. 57, 58 p45/v2, p44/v1 f lcd driving power supply pins these pins can be used as an n-ch open-drain general-purpose i/o when not used as an lcd driving power supply. 59 to 62 p43/com3 to p40/com0 f lcd common output pins these pins can be used as an n-ch open-drain general-purpose i/o when not used as an lcd common output. 63 to 70 p50/seg0 to p57/seg7 f lcd segment output pins these pins can be used as an n-ch open-drain general-purpose i/o when not used as an lcd segment output. 71 to 78 p60/seg8 to p67/seg15 f lcd segment output pins these pins can be used as an n-ch open-drain general-purpose i/o when not used as an lcd segment output. 79, 80 p70/seg16, p71/seg17 f lcd segment output pins these pins can be used as an n-ch open-drain general-purpose i/o when not used as an lcd segment output. 1 to 6 p72/seg18 to p77/seg23 f lcd segment output pins these pins can be used as an n-ch open-drain general-purpose i/o when not used as an lcd segment output. 7 to 11 p80/seg24 to p83/seg27 f lcd segment output pins these pins can be used as an n-ch open-drain general-purpose i/o when not used as an lcd segment output. 52 av ss ? a/d converter power supply (gnd) pin 53 avr ? a/d converter reference power supply pin 54 av cc ? a/d converter power supply pin 55 v cc ? power supply pin 56 v3 ? lcd driving power supply pin 15 v ss ? power supply (gnd) pin
9 mb89920 series ? external eprom pins (the mb89pv920 only) pin no. pin name i/o function 82 83 84 85 86 87 88 89 90 91 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 o address output pins 93 94 95 o1 o2 o3 i data input pins 96 v ss o power supply (gnd) pin 98 99 100 101 102 o4 o5 o6 o7 o8 i data input pins 103 ce o rom chip enable pin outputs h during standby. 104 a10 o address output pin 105 oe /v pp o rom output enable pin outputs l at all times. 107 108 109 a11 a9 a8 o address output pins 110 a13 o address output pin 111 a14 o address output pin 112 v cc o eprom power supply pin 81 92 97 106 n.c. internally connected pins be sure to leave them open.
10 mb89920 series n i/o circuit type (continued) type circuit remarks a ? at an oscillation feedback resistor of approximately 1 m w (1 to 8 mhz) b c ? at an output pull-up resistor of approximately 50 k w (5.0 v) ? hysteresis input d ? cmos output ? cmos input ? pull-up resistor optional e ? cmos output ? cmos input ? hysteresis input (peripheral input) ? pull-up resistor optional x1 x0 standby control signal p-ch r n-ch r p-ch n-ch p-ch n-ch p-ch p-ch r
11 mb89920 series (continued) type circuit remarks f ? n-ch open-drain i/o ? also serves as lcd controller/driver common/ segment output. g ? cmos i/o ? analog input p-ch n-ch p-ch n-ch n-ch n-ch p-ch analog input
12 mb89920 series n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on 1. absolute maximum ratings in section n electrical characteristics is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also, take care to prevent the analog power supply (av cc and avr) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. treatment of power supply pins on microcontrollers with a/d and d/a converters connect to be av cc = davc = v cc and av ss = avr = v ss even if the a/d and d/a converters are not in use. 4. treatment of n.c. pins be sure to leave (internally connected) n.c. pins open. 5. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. 6. precautions when using an external clock even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode.
13 mb89920 series n programming to the eprom on the mb89p928 the mb89p928 is an otprom version of the mb89920 series. 1. features ? 48-kbyte prom on chip ? options can be set using the eprom programmer. ? equivalency to the mbm27c1001a in eprom mode (when programmed with the eprom programmer) 2. memory space memory space in the eprom mode is diagrammed below. ffff h program area (eprom) ffff h ram rom i/o normal operating mode eprom mode (corresponding addresses on the eprom programmer) not available 0000 h 4000 h 0480 h 0080 h 0000 h 4000 h address register 0100 h 0200 h option area vacancy (read value undefined) vacancy (read value undefined) 0fe4 h 1000 h vacancy (read value undefined) 1fff h
14 mb89920 series 3.programming to the eprom in eprom mode, the mb89p928 functions equivalent to the mbm27c1001a. this allows the prom to be programmed with a general-purpose eprom programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. ? programming procedure (1) set the eprom programmer to the mbm27c1001a. (2) load program data into the eprom programmer at 0fe4 h to ffff h . (3) program with the eprom programmer. 4. recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked otprom microcomputer program. 5. programming yield all bits cannot be programmed at fujitsu shipping test to a blanked otprom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times. 6. eprom programmer socket adapter inquiry: sun hayato co., ltd.: tel 81-3-3802-5760 note: depending on the eprom programmer, inserting a capacitor of about 0.1 m f between v pp and v ss or v cc and v ss can stabilize programming operations. package compatible socket adapter fpt-80p-m06 rom-80qf-32dp-8la program, verify aging +150 c, 48 hrs. data verification assembly
15 mb89920 series 7. prom option bit map notes: set each bit to 1 to erase. do not write 0 to the vacant bit. the read value of the vacant bit is 1, unless 0 is written to it. ? write the same value as each option register to the 3-byte vacant address that follows above option registers. example: in the case of 0fe4 h , write the same value to 0fe5 h , 0fe6 h and 0ff7 h . ? this optional information is taken into the otprom while the oscillation is being reset. therefore, if the hardware state is initially shifted to standby state after the power supply is turned on, the optional information will not be valid during the transition (in a state of the initial value 1). after the hardware standby state is cleared, the oscillation starts and the optional information becomes valid. note that if the hardware is shifted to the standby or stop state in the course of a normal operation (oscillation), the contents of the optional register are valid since the option data has already been taken into the otprom. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0fe4 h vacancy readable vacancy readable vacancy readable oscillation stabilization time 1: crystal 0: ceramic reset pin output 1: yes 0: no power-on reset 1: yes 0: no vacancy readable vacancy readable 0fe8 h p07 pull-up 1: no 0: yes p06 pull-up 1: no 0: yes p05 pull-up 1: no 0: yes p04 pull-up 1: no 0: yes p03 pull-up 1: no 0: yes p02 pull-up 1: no 0: yes p01 pull-up 1: no 0: yes p00 pull-up 1: no 0: yes 0fec h p27 pull-up 1: no 0: yes p26 pull-up 1: no 0: yes p25 pull-up 1: no 0: yes p24 pull-up 1: no 0: yes p23 pull-up 1: no 0: yes p22 pull-up 1: no 0: yes p21 pull-up 1: no 0: yes p20 pull-up 1: no 0: yes 0ff0 h vacancy readable vacancy readable vacancy readable vacancy readable vacancy readable p32 pull-up 1: no 0: yes p31 pull-up 1: no 0: yes p30 pull-up 1: no 0: yes 0ff4 h p97 pull-up 1: no 0: yes p96 pull-up 1: no 0: yes p95 pull-up 1: no 0: yes p94 pull-up 1: no 0: yes p93 pull-up 1: no 0: yes p92 pull-up 1: no 0: yes p91 pull-up 1: no 0: yes p90 pull-up 1: no 0: yes 0ff8 h vacancy readable vacancy readable wdt/low- voltage control 1: register 0: option eprom low-voltage detection voltage low-voltage reset 1: yes 0: no low-voltage detection 1: automatic 0: prohibited watchdog timer (wdt) 1: automatic 0: prohibited 00: 01: 3.3 v 10: 3.6 v 11: 4.0 v 0ffc h vacancy readable vacancy readable vacancy readable vacancy readable vacancy readable vacancy readable vacancy readable vacancy readable
16 mb89920 series n programming to the eprom with piggyback/evaluation device 1. eprom for use mbm27c512-20tv 2. programming socket adapter to program to the prom using an eprom programmer, use the socket adapter (manufacturer: sun hayato co., ltd.) listed below. inquiry: sun hayato co., ltd.: tel 81-3-3802-5760 3. memory space memory space in each mode is diagrammed below. 4. programming to the eprom (1) set the eprom programmer to the mbm27c512. (2) load program data into the eprom programmer at 4000 h to ffff h . (3) program to 4000 h to ffff h with the eprom programmer. package adapter socket part number lcc-32(rectangle) rom-32lc-28dp-yg lcc-32(square) rom-32lc-28dp-s 4000 h ffff h not available eprom 48 kb ffff h ram prom 48 kb i/o normal operating mode corresponding addresses on the eprom programmer not available 0000 h 4000 h 0480 h 0080 h 0000 h address
17 mb89920 series n block diagram ram cpu rom x0 x1 f 2 mc-8l 4 4 p91/rto1 p90/rto0 p32/uck p31/uo p30/ui p94/pwm1 p93/pwm0 p92/clk oscillator clock control rst hst reset circuit watchdog timer low-voltage detection n-ch open-drain i/o port lcd controller /driver n-ch open-drain i/o port p80/seg24 to p83/seg27 8 p70/seg16 to p77/seg23 8 p60/seg8 to p67/seg15 8 p50/seg0 to p57/seg7 v3 28 2 2 p44/v1, p45/v2 4 4 p40/com0 to p43/com3 cmos i/o port cmos i/o port external interrupt 6 p21 to p22 p24 to p27 4 p04 to p07 4 p00/int0 to p03/int3 internal bus operating mode control time-base timer moda cmos i/o port output compare 16-bit free run counter input capture uart p23/rti1 p20/rti0 p95/sck p96/so p97/si serial i/o 2-channel 8-bit pwm timer 8-bit timer #2 8-bit timer #1 cmos i/o port buzzer/clock output 10-bit a/d converter avr 8 p10/an0 to p17/an7 8
18 mb89920 series n cpu core 1. memory space the microcontrollers of the mb89920 series offer a memory space of 64 kbytes for storing all of i/o, data, and program areas. the i/o area is located at the lowest address. the data area is provided immediately above the i/o area. the data area can be divided into register, stack, and direct areas according to the application. the program area is located at exactly the opposite end, that is, near the highest address. provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. the memory space of the mb89920 series is structured as illustrated below. memory space rom ffff h 0080 h 0000 h i/o mb89923 e000 h 0100 h ffff h 0080 h 0000 h i/o 0100 h ffff h 0080 h 0000 h i/o 0100 h 0200 h 0480 h ram register ram ram 0200 h 0180 h 0280 h not available c000 h 4000 h program rom rom not available register register not available ffff h 0080 h 0000 h i/o 0100 h 0200 h 0480 h ram 4000 h program rom register not available mb89925 mb89p928 mb89pv920
19 mb89920 series 2. registers the f 2 mc-8l family has two types of registers; dedicated registers in the cpu and general-purpose registers in the memory. the following dedicated registers are provided: program counter (pc): a 16-bit register for indicating instruction storage positions accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a 16-bit register which performs arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a 16-bit register for index modification extra pointer (ep): a 16-bit pointer for indicating a memory address stack pointer (sp): a 16-bit register for indicating a stack area program status (ps): a 16-bit register for storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr). (see the diagram below.) pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h undefined undefined undefined undefined undefined i-flag = 0, il1, 0 = 11 other bits are undefined. initial value structure of the program status register vacancy h i il1, 0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr vacancy vacancy
20 mb89920 series the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of cpu operations at the time of an interrupt. h-flag: set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared otherwise. this flag is for decimal adjustment instructions. i-flag: interrupt is allowed when this flag is set to 1. interrupt is prohibited when the flag is set to 0. set to 0 when reset. il1, 0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-flag: set if the msb is set to 1 as the result of an arithmetic operation. cleared when the bit is set to 0. z-flag: set when an arithmetic operation results in 0. cleared otherwise. v-flag: set if the complement on 2 overflows as a result of an arithmetic operation. reset if the overflow does not occur. c-flag: set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared otherwise. set to the shift-out value in the case of a shift instruction. il1 il0 interrupt level high-low 00 1 high low = no interrupt 01 10 2 11 3 rule for conversion of actual addresses of the general-purpose register area ? a15 ? a14 ? a13 ? a12 ? a11 ? a10 ? a9 ? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 lower op codes rp generated addresses
21 mb89920 series the following general-purpose registers are provided: general-purpose registers: an 8-bit register for storing data the general-purpose registers are 8 bits and located in the register banks of the memory. one bank contains eight registers and up to a total of 16 banks can be used on the mb89925. up to a total of 16 banks can be used on the mb89923. the bank currently in use is indicated by the register bank pointer (rp). note: the number of register banks that can be used varies with the ram size. r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7 this address = 0100 h + 8 (rp) memory area 32 banks register bank configuration
22 mb89920 series n i/o map (continued) C: unused x: undefined note: do not use vacancies address read/write register register description intial value 00 h (r/w) pdr0 port 0 data register x x x x x x x x b 01 h (w) ddr0 port 0 data direction register 0 0 0 0 0 0 0 0 b 02 h (r/w) pdr1 port 1 data register x x x x x x x x b 03 h (w) ddr1 port 1 data direction register 0 0 0 0 0 0 0 0 b 04 h vacancy 05 h vacancy 06 h vacancy 07 h vacancy 08 h (r/w) stbc standby control register 0 0 0 1 x x x x b 09 h (r/w) wdte watchdog timer control register x x x x x x x x b 0a h (r/w) tbcr time-base timer control register x x x 0 0 0 0 0 b 0b h (r/w) lvrc low-voltage detection reset control register 0 x 1 1 x 0 0 x b 0c h (r/w) pdr3 port 3 data/peripheral i/o control register 0 0 0 0 C x x x b 0d h (w) ddr3 port 3 data direction register C C C C C 0 0 0 b 0e h (r/w) pdr4 port 4 data register C C 1 1 1 1 1 1 b 0f h (r/w) pdr5 port 5 data register 1 1 1 1 1 1 1 1 b 10 h (r/w) pdr6 port 6 data register 1 1 1 1 1 1 1 1 b 11 h (r/w) pdr7 port 7 data register 1 1 1 1 1 1 1 1 b 12 h (r/w) pdr8 port 8 data register C C C C 1 1 1 1 b 13 h (r/w) pdr9 port 9 data register x x x x x x x x b 14 h (w) ddr9 port 9 data direction register 0 0 0 0 0 0 0 0 b 15 h (r/w) pdr2 port 2 data register x x x x x x x x b 16 h (r/w) ddr2 port 2 data direction register 0 0 0 0 0 0 0 0 b 17 h (r/w) buzr buzzer control register x x x x 0 0 0 0 b 18 h (r/w) adc1 ad converter control register 1 0 0 0 0 0 0 0 0 b 19 h (r/w) adc2 ad converter control register 2 x 0 0 0 0 0 0 1 b 1a h (r/w) adch ad converter data register h C C C C C C x x b 1b h (r/w) adcl ad converter data register l x x x x x x x x b 1c h (r/w) smr serial mode register 0 0 0 0 0 0 0 0 b 1d h (r/w) sdr serial data register x x x x x x x x b 1e h vacancy 1f h (w) icr1 port 1 input control register 0 0 0 0 0 0 0 0 b
23 mb89920 series (continued) C: unused x: undefined note: do not use vacancies address read/write register register description initial value 20 h (r/w) cntr1 pwm timer control register 1 0 0 0 0 0 0 0 0 b 21 h (r/w) cntr2 pwm timer control register 2 0 0 0 0 0 0 0 0 b 22 h (r/w) cntr3 pwm timer control register 3 0 0 0 x 0 0 0 0 b 23 h (w) comr2 pwm timer compare register 2 x x x x x x x x b 24 h (w) comr1 pwm timer compare register 1 x x x x x x x x b 25 h vacancy 26 h vacancy 27 h vacancy 28 h (r/w) tmcr timer control register 0 0 x x 0 0 0 0 b 29 h (r) tchr timer count register (h) 0 0 0 0 0 0 0 0 b 2a h (r) tclr timer count register (l) 0 0 0 0 0 0 0 0 b 2b h (r/w) opcr output control register 0 0 0 0 0 0 0 0 b 2c h (r/w) cpr0h output compare register 0 (h) 0 0 0 0 0 0 0 0 b 2d h (r/w) cpr0l output compare register 0 (l) 0 0 0 0 0 0 0 0 b 2e h (r/w) cpr1h output compare register 1 (h) 0 0 0 0 0 0 0 0 b 2f h (r/w) cpr1l output compare register 1 (l) 0 0 0 0 0 0 0 0 b 30 h (r/w) iccr input capture control register x 0 0 0 x 0 0 0 b 31 h (r/w) icic input capture interrupt control register x 0 0 0 0 x 0 0 b 32 h (r) icr0h input capture register 0 (h) x x x x x x x x b 33 h (r) icr0l input capture register 0 (l) x x x x x x x x b 34 h (r) icr1h input capture register 1 (h) x x x x x x x x b 35 h (r) icr1l input capture register 1 (l) x x x x x x x x b 36 h vacancy 37 h vacancy 38 h (r/w) eic1 external interrupt control register 1 0 0 0 0 0 0 0 0 b 39 h (r/w) eic2 external interrupt control register 2 0 0 0 0 0 0 0 0 b 3a h vacancy 3b h vacancy 3c h vacancy 3d h vacancy 3e h vacancy 3f h vacancy
24 mb89920 series (continued) C: unused x: undefined note: do not use vacancies address read/write register register description initial value 40 h (r/w) usmr uart mode register 0 0 0 0 0 0 0 0 b 41 h (r/w) uscr uart control register 0 0 0 0 0 0 0 0 b 42 h (r/w) ustr uart status register 0 0 0 0 1 x x x b 43 h (r) (w) rxdr txdr uart receiver data register uart transmitter data register x x x x x x x x b x x x x x x x x b 44 h vacancy 45 h (r/w) rrdr baud rate generator/reload data register x x x x x x x x b 46 h vacancy 47 h vacancy 48 to 5f h vacancy 60 to 6d h (r/w) vram display data ram x x x x x x x x b 70 h (r/w) lcr1 lcd controller/driver control register 1 0 0 0 0 0 0 0 0 b 71 h (r/w) lcr2 lcd controller/driver control register 2 0 0 0 C C C C C b 72 h (r/w) lcr3 lcd controller/driver control register 3 0 0 0 0 0 0 0 0 b 73 to 7b h vacancy 7c h (w) ilr1 interrupt level setting register 1 1 1 1 1 1 1 1 1 b 7d h (w) ilr2 interrupt level setting register 2 1 1 1 1 1 1 1 1 b 7e h (w) ilr3 interrupt level setting register 3 1 1 1 1 1 1 1 1 b 7f h vacancy
25 mb89920 series n electrical characteristics 1. absolute maximum ratings (v ss = 0.0 v) *1: use av cc and v cc set at the same voltage. take care so that av cc does not exceed v cc , such as when power is turned on. *2: v cc must not exceed v3. precautions: permanent device damage may occur if the above absolute maximum ratings are exceeded. func- tional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol value unit remarks min. max. power supply voltage v cc v ss C 0.3 v ss + 7.0 v av cc v ss C 0.3 v cc + 0.3 v * 1 avr v ss C 0.3 v ss + 7.0 v avr must not exceed av cc + 0.3 v. lcd power supply voltage v1 to v3 v ss C 0.3 v ss + 7.0 v v1 v2 v3 * 2 input voltage v i1 v ss C 0.3 v cc + 0.3 v output voltage v o1 v ss C 0.3 v cc + 0.3 v p00 to p07, p10 to p17, p20 to p27, p30 to p32, p90 to p97 v o2 v ss C 0.3 v ss + 7.0 v p40 to p45, p50 to p57, p60 to p67, p70 to p77, p80 to p83 must not exceed v3 + 0.3 v l level maximum output current i ol ? 20 ma peak value l level average output current i olav ? 4 ma average value l level total maximum output current ? i ol ? 100 ma peak value l level total average output current ? i olav ? 40 ma average value h level maximum output current i oh ? C20 ma peak value h level average output current i ohav ? C4 ma average value h level total maximum output current ? i oh ? C50 ma peak value h level total average output current ? i ohav ? C20 ma average value power consumption p d ? 300 mw operating temperature t a C40 +85 c storage temperature tstg C55 +150 c
26 mb89920 series 2. recommended operating conditions (v ss = 0.0 v) *1: these values vary with the operating frequency, instruction cycle, and analog assurance range. see figure 1 and 5. a/d converter electrical characteristics. *2: v cc must not exceed v3. figure 1 operating voltage vs. clock operating frequency figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/f c . since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. parameter symbol value unit remarks min. max. power supply voltage v cc 2.2* 1 6.0 v normal operation assurance range 2.7* 1 6.0 v mb89pv920/p928 1.5 6.0 v retains the ram state in stop mode a/d converter reference input voltage avr 3.0 av cc v lcd power supply voltage v1 to v3 v ss v ss + 6.0 v v1 v2 v3* 2 operating temperature t a C40 +85 c 4.0 0.8 0.5 2.0 1 2 3 4 5 6 1.0 5.0 8.0 operating voltage (v) operation assurance range clock operating frequency (at an instruction cycle of 4/f c ) (mhz) note: the shaded area is assured only for the mb89923/925. minimum execution time (instruction cycle) ( m s) 2.0 3.0 4.0 6.0 7.0 10.0 9.0 analog accuracy assured in the av cc = 3.5 v to 6.0 v range
27 mb89920 series 3. dc characteristics (v cc = 5.0 v, v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter sym- bol pin condition value unit remarks min. typ. max. h level input voltage v ih p00 to p07, p10 to p17, p20 to p27, p30 to p32, p40 to p45, p50 to p57, p60 to p67, p70 to p77, p80 to p83, p90 to p97 0.7 v cc v cc + 0.3 v v ihs rst , moda, hst 0.8 v cc v cc + 0.3 v peripheral input of the port 0, 2, 3, and 9 l level input voltage v il p00 to p07, p10 to p17, p20 to p27, p30 to p32, p40 to p45, p50 to p57, p60 to p67, p70 to p77, p80 to p83, p90 to p97 v ss - 0.3 0.3 v cc v v ils rst , moda, hst v ss - 0.3 0.2 v cc v peripheral input of the port 0, 2, 3, and 9 open-drain output pin application voltage v d p40 to p45, p50 to p57, p60 to p67, p70 to p77, p80 to p83 *1 v ss - 0.3 v ss + 6.0 v h level output voltage v oh1 p00 to p07, p10 to p17, p30 to p32, p90 to p97 i oh = C2.0 ma 4.0 v v oh2 p20 to p27 i oh = C5.0 ma 2.4 v l level output voltage v ol1 p00 to p07, p10 to p17, p30 to p32, p40 to p45, p50 to p57, p60 to p67, p70 to p77, p80 to p83, p90 to p97 i ol = 4.0 ma 0.4 v v ol2 p20 to p27 i ol = 5.0 ma 0.4 v v ol3 rst i ol = 4.0 ma 0.4 v input leakage current (hi-z output leakage current) i li1 p00 to p07, p10 to p17, p20 to p27, p30 to p32, p40 to p45, p50 to p57, p60 to p67, p70 to p77, p80 to p83, p90 to p97, moda 0.45 v < v i < v cc 5 m a without pull- up resistor pull-up resistance r pulu p00 to p07, p20 to p27, p30 to p32, p90 to p97 v i = 0.0 v 25 50 100 k w without pull- up resistor
28 mb89920 series (v cc = 5.0 v, v ss = 0.0 v, t a = C40 c to +85 c) *1: v d must not exceed v3. *2: the measurement conditions of power supply current are as follows: the external clock and t a = +25 c. in the case of the mb89pv920, the current consumed by the connected eprom and ice is not included. note: for pins which serve as the lcd and ports (p40 to p45, p50 to p57, p60 to p67, p70 to p77, and p80 to p83), see the port parameter when these pins are used as ports and the lcd parameter when they are used as lcd pins. parameter sym- bol pin condition value unit remarks min. typ. max. power supply current *2 i cc v cc v cc = 5.0 v 12 20 ma t inst = 0.5 m s i ccs v cc = 5.0 v 3 7 ma sleep mode t inst = 0.5 m s i cch t a = +25 c1 m a stop mode i a av cc when a/d conversion is activated 6 8ma i ah when a/d conversion is stopped t a = +25 c 1 m a lcd divided resistance r lcd between v3 and v ss 200 300 450 k w com0 to 3 output impedance r vcom com0 to 3 v1 to v 3 = 5.0 v 2.5 k w seg0 to 27 output impedance r vseg seg0 to 27 v1 to v 3 = 5.0 v 15 k w lcd controller/ driver leakage current i lcdl v1 to v3, com0 to 3, seg0 to 27 v1 to v 3 = 5.0 v 1 m a input capacitance c in other than av cc , av ss , v cc , and v ss f = 1 mhz 10 pf
29 mb89920 series 4. ac characteristics (1) reset timing (av ss = v ss = 0.0 v, t a = C40 c to +85 c) (2) power-on reset (av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: make sure that power supply rises within the selected oscillation stabilization time. if power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. parameter symbol condition value unit remarks min. max. rst l pulse width t zlzh 48 t hcyl ns parameter symbol condition value unit remarks min. max. power supply rising time t r 50 ms power-on reset function only power supply cut-off time t off 1 ms due to repeated operations 0.2 v cc 0.2 v cc rst t zlzh 0.2 v 0.2 v 2.0 v v cc 0.2 v t r t off
30 mb89920 series (3) clock timing (av ss = v ss = 0.0 v, t a = C40 c to +85 c) (4) instruction cycle parameter symbol pin condition value unit remarks min. max. clock frequency f c x0, x1 18mhz clock cycle time t xcyl x0, x1 125 1000 ns input clock pulse width p wh p wl x0 20 ns external clock input clock rising/falling time t cr t cf x0 10 ns external clock parameter symbol value (typical) unit remarks instruction cycle (minimum execution time) t inst 4/f c m s (4/f c ) t inst = 0.5 m s when operating at f c = 8 mhz 0.2 v cc 0.8 v cc x0 0.2 v cc t cr t cf 0.8 v cc 0.2 v cc x0 x1 x0 x1 t xcyl f c c1 c2 when a crystal or ceramic resonator is used when an external clock is used open p wh p wl x0 and x1 timing and conditions clock conditions
31 mb89920 series (5) serial i/o timing (av cc = v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin condition value unit remarks min. max. serial clock cycle time t scyc sck internal shift clock mode 2 t inst * m s sck ? so time t slov sck, so C200 200 ns valid si ? sck - t ivsh si, sck 1/2 t inst * m s sck - ? valid si hold time t shix sck, si 1/2 t inst * m s serial clock h pulse width t shsl sck external shift clock mode 1 t inst * m s serial clock l pulse width t slsh sck 1 t inst * m s sck ? so time t slov sck, so 0 200 ns valid si ? sck - t ivsh si, sck 1/2 t inst * m s sck - ? valid si hold time t shix sck, si 1/2 t inst * m s 0.8 v 2.4 v t scyc 2.4 v 0.2 v cc t shix 0.8 v 0.8 v t ivsh 0.8 v cc 0.2 v cc 0.8 v cc sck so si t slov t slsh 2.4 v t shix 0.8 v cc 0.8 v t ivsh 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc t shsl 0.8 v cc 0.2 v cc 0.2 v cc sck so si t slov internal shift clock mode external shift clock mode
32 mb89920 series (6) peripheral input timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin value unit remarks min. max. peripheral input h pulse width 1 t ilih1 int0 to int3, rti0, 1 2 t inst * peripheral input l pulse width 1 t ihil1 int0 to int3, rti0, 1 2 t inst * 0.2 v cc 0.8 v cc t ihil1 0.8 v cc rti0, 1 int0 to 3 0.2 v cc t ilih1
33 mb89920 series 5. a/d converter electrical characteristics (av cc = v cc = +3.5 v to +6.0 v, f c = 8 mh z , av ss = v ss = 0.0 v, t a = C40 c to +85 c) precautions: ? the smaller | avr C av ss |, the greater the error would become relatively. ? the output impedance of the external circuit for the analog input must satisfy the following conditions: output impedance of the external circuit < approx. 10 k w if the output impedance of the external circuit is too high, an analog voltage sampling time might be insufficient (sampling time = 7.5 m s at 8 mhz oscillation). an analog input equivalent circuit is shown below. since the a/d converter contains sample hold circuit, the level of the analog input pin might not stabilize within the sampling period after a/d activation, resulting in inaccurate a/d conversion values, if the input impedance to the analog pin is too high. be sure to maintain an appropriate input impedance to the analog pin. it is recommended to keep the input impedance to the analog pin not exceed 10 k w . if it exceeds 10 k w , it is recommended to connect a capacitor of about 0.1 m f for the analog input pin. except for the sampling period after a/d activation, the input leakage current of the analog input pin is less than 10 m a. parameter sym- bol pin condition value unit min. typ. max. resolution av cc = avr = v cc 10 bit linearity error 2.0 lsb differential linearity error 1.5 lsb differential total error 3.0 lsb zero transition voltage v ot an0 to an7 av ss C 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb mv full-scale transition voltage v fst an0 to an7 avr C 3.5 lsb avr C 1.5 lsb avr + 0.5 lsb mv interchannel disparity 4lsb a/d mode conversion time 16.5 m s analog port input current v ain an0 to an7 at 8-mh z oscillattion 10 m a analog input voltage an0 to an7 0.0 avr v reference voltage avr 0.0 av cc v reference voltage supply current i r avr avr = 5.0 v 200 ?m a comparator c = 60 pf r = 3 k w ( ) sample hold circuit close for approx. 15 instruction cycles after activating a/d conversion. analog channel selector r 10 k w is recommended. an if r > 10 k w , it is recommended to connect an external capacitor of approx. 0.1 m f. microcontrollers internal circuit . . . .
34 mb89920 series (1) a/d converter glossary ? resolution analog changes that are identifiable with the a/d converter. ? linearity error the deviation of the straight line connecting the zero transition point (00 0000 0000 ? 00 0000 0001) with the full-scale transition point (11 1111 1111 ? 11 1111 1110) from actual conversion characteristics ? differential linearity error the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value ? total error the difference between theoretical and actual conversion values, caused by the zero transition error, full-scale transition error, linearity error, quantization error, and noise. (continued) 3ff 3fe 3fd 004 003 002 001 v ot 0.5 lsb av ss 1 lsb 1.5 lsb v fst avr 3ff 3fe 3fd 004 003 002 001 av ss v nt avr {1 lsb n + 0.5 lsb} 1 lsb = v fst - v ot 1022 (v) v nt - {1 lsb n + 0.5 lsb} 1 lsb theoreticall i/o characteristics digital output analog input digital output total error actual conversion value actual conversion value theoretical value analog input total error of digital output n =
35 mb89920 series (continued) 3ff 3fe 3fd 004 003 002 001 av ss v nt avr {1 lsb n + v ot } v nt ?{1 lsb n + v ot } 1 lsb 004 003 002 001 av ss 3ff 3fe 3fd 3fc avr av ss avr v nt v (n+1)t ?v nt 1 lsb ?1 zero transition error digital output analog input actual conversion value theoretical value actual conversion value v ot (actual measured value) full-scale transition error digital output analog input actual conversion value actual conversion value v fst (actual measured value) theoretical value differential linearity error digital output analog input v (n + 1)t actual conversion value actual conversion value theoretical value n + 1 n n 1 n 2 linearity error digital output analog input v ot (actual measured value) v fst (actual measured value) actual conversion value theoretical value actual conversion value linearity error of digital output n = differential linearity error of digital output n =
36 mb89920 series 6. low-voltage detection reset (av ss = v ss = 0.0 v, t a = C40 c to +85 c) *1: vdh and vdl can be set for the mb89923 and mb89925 by mask options; for the mb89pv920 and mb89p928 by registers. parameter symbol condition value unit remarks min. max. voltage detected at power supply voltage drop v dl1 3.00 3.60 v * 1 v dl2 3.30 3.90 v v dl3 3.70 4.30 v voltage detected at power supply voltage rise v dh1 3.10 3.80 v v dh2 3.40 4.10 v v dh3 3.80 4.50 v hysteresis width d v0.10v reset ignore time t l 0.3 m s reset sense time t lw 16 t xcyl ns reset detection deley time t d 2.0 m s voltage regulation (v d /t d )vcr 0.10v/ m s t d v cc v d d v power supply voltage v dh * v dl * power supply voltage run reset t osc oscillation stabilization time 2 19 = 65.5 ms (f = 8 mhz) t d t d v cc v dh * v dl * run reset not reset reset less than t l over than t lw t t t osc t osc
37 mb89920 series n instructions (136 instructions) execution instructions can be divided into the following four groups: ? transfer ? arithmetic operation ? branch ? others table 1 lists symbols used for notation of instructions. table 1 instruction symbols columns indicate the following: mnemonic: assembler notation of an instruction ~: the number of instructions #: the number of bytes operation: operation of an instruction tl, th, ah: a content change when each of the tl, th, and ah instructions is executed. symbols in the column indicate the following: ? C indicates no change. ? dh is the 8 upper bits of operation description data. ? al and ah must become the contents of al and ah prior to the instruction executed. ? 00 becomes 00. n, z, v, c: an instruction of which the corresponding flag will change. if + is written in this column, the relevant instruction will change its corresponding flag. op code: code of an instruction. if an instruction is more than one code, it is written according to the following rule: example: 48 to 4f ? this indicates 48, 49, ... 4f. symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8:3 bits) rel branch relative address (8 bits) @ register indirect (example: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of accumulator a (8 bits) al lower 8 bits of accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of temporary accumulator t (8 bits) tl lower 8 bits of temporary accumulator t (8 bits) ix index register ix (16 bits) ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits) rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) ( ) indicates that the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (( )) the address indicated by the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.)
38 mb89920 series table 2 transfer instructions (48 instructions) note during byte transfer to a, t ? a is restricted to low bytes. operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (reverse arrangement of f 2 mc-8 family) mnemonic ~ # operation tl th ah n z v c op code mov dir,a mov @ix +off,a mov ext,a mov @ep,a mov ri,a mov a,#d8 mov a,dir mov a,@ix +off mov a,ext mov a,@a mov a,@ep mov a,ri mov dir,#d8 mov @ix +off,#d8 mov @ep,#d8 mov ri,#d8 movw dir,a movw @ix +off,a movw ext,a movw @ep,a movw ep,a movw a,#d16 movw a,dir movw a,@ix +off movw a,ext movw a,@a movw a,@ep movw a,ep movw ep,#d16 movw ix,a movw a,ix movw sp,a movw a,sp mov @a,t movw @a,t movw ix,#d16 movw a,ps movw ps,a movw sp,#d16 swap setb dir: b clrb dir: b xch a,t xchw a,t xchw a,ep xchw a,ix xchw a,sp movw a,pc 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ? (a) ( (ix) +off ) ? (a) (ext) ? (a) ( (ep) ) ? (a) (ri) ? (a) (a) ? d8 (a) ? (dir) (a) ? ( (ix) +off) (a) ? (ext) (a) ? ( (a) ) (a) ? ( (ep) ) (a) ? (ri) (dir) ? d8 ( (ix) +off ) ? d8 ( (ep) ) ? d8 (ri) ? d8 (dir) ? (ah),(dir + 1) ? (al) ( (ix) +off) ? (ah), ( (ix) +off + 1) ? (al) (ext) ? (ah), (ext + 1) ? (al) ( (ep) ) ? (ah),( (ep) + 1) ? (al) (ep) ? (a) (a) ? d16 (ah) ? (dir), (al) ? (dir + 1) (ah) ? ( (ix) +off), (al) ? ( (ix) +off + 1) (ah) ? (ext), (al) ? (ext + 1) (ah) ? ( (a) ), (al) ? ( (a) ) + 1) (ah) ? ( (ep) ), (al) ? ( (ep) + 1) (a) ? (ep) (ep) ? d16 (ix) ? (a) (a) ? (ix) (sp) ? (a) (a) ? (sp) ( (a) ) ? (t) ( (a) ) ? (th),( (a) + 1) ? (tl) (ix) ? d16 (a) ? (ps) (ps) ? (a) (sp) ? d16 (ah) ? (al) (dir): b ? 1 (dir): b ? 0 (al) ? (tl) (a) ? (t) (a) ? (ep) (a) ? (ix) (a) ? (sp) (a) ? (pc) C C C C C al al al al al al al C C C C C C C C C al al al al al al C C C C C C C C C C C C C C C al al C C C C C C C C C C C C C C C C C C C C C C C C C ah ah ah ah ah ah C C C C C C C C C C C C C C C C ah C C C C C C C C C C C C C C C C C C C C C C C C C dh dh dh dh dh dh dh C C dh C dh C C C dh C C al C C C dh dh dh dh dh C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 45 46 61 47 48 to 4f 04 05 06 60 92 07 08 to 0f 85 86 87 88 to 8f d5 d6 d4 d7 e3 e4 c5 c6 c4 93 c7 f3 e7 e2 f2 e1 f1 82 83 e6 70 71 e5 10 a8 to af a0 to a7 42 43 f7 f6 f5 f0
39 mb89920 series table 3 arithmetic operation instructions (62 instructions) (continued) mnemonic ~ # operation tl th ah n z v c op code addc a,ri addc a,#d8 addc a,dir addc a,@ix +off addc a,@ep addcw a addc a subc a,ri subc a,#d8 subc a,dir subc a,@ix +off subc a,@ep subcw a subc a inc ri incw ep incw ix incw a dec ri decw ep decw ix decw a mulu a divu a andw a orw a xorw a cmp a cmpw a rorc a rolc a cmp a,#d8 cmp a,dir cmp a,@ep cmp a,@ix +off cmp a,ri daa das xor a xor a,#d8 xor a,dir xor a,@ep xor a,@ix +off xor a,ri and a and a,#d8 and a,dir 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (a) ? (a) + (ri) + c (a) ? (a) + d8 + c (a) ? (a) + (dir) + c (a) ? (a) + ( (ix) +off) + c (a) ? (a) + ( (ep) ) + c (a) ? (a) + (t) + c (al) ? (al) + (tl) + c (a) ? (a) - (ri) - c (a) ? (a) - d8 - c (a) ? (a) - (dir) - c (a) ? (a) - ( (ix) +off) - c (a) ? (a) - ( (ep) ) - c (a) ? (t) - (a) - c (al) ? (tl) - (al) - c (ri) ? (ri) + 1 (ep) ? (ep) + 1 (ix) ? (ix) + 1 (a) ? (a) + 1 (ri) ? (ri) - 1 (ep) ? (ep) - 1 (ix) ? (ix) - 1 (a) ? (a) - 1 (a) ? (al) (tl) (a) ? (t) / (al),mod ? (t) (a) ? (a) (t) (a) ? (a) (t) (a) ? (a) " (t) (tl) - (al) (t) - (a) (a) - d8 (a) - (dir) (a) - ( (ep) ) (a) - ( (ix) +off) (a) - (ri) decimal adjust for addition decimal adjust for subtraction (a) ? (al) " (tl) (a) ? (al) " d8 (a) ? (al) " (dir) (a) ? (al) " ( (ep) ) (a) ? (al) " ( (ix) +off) (a) ? (al) " (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) C C C C C C C C C C C C C C C C C C C C C C C dl C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 00 C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C dh C C C C dh C C C dh dh 00 dh dh dh C C C C C C C C C C C C C C C C C C C C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + C C C C C C C C C + + C C + + + C C C C C C C C C + + C C C C C C C C C C + + r C + + r C + + r C + + + + + + + + + + C + + + C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C 28 to 2f 24 25 26 27 23 22 38 to 3f 34 35 36 37 33 32 c8 to cf c3 c2 c0 d8 to df d3 d2 d0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1f 84 94 52 54 55 57 56 58 to 5f 62 64 65 a c ? ? ?? a c
40 mb89920 series (continued) table 4 branch instructions (17 instructions) table 5 other instructions (9 instructions) mnemonic ~ # operation tl th ah n z v c op code and a,@ep and a,@ix +off and a,ri or a or a,#d8 or a,dir or a,@ep or a,@ix +off or a,ri cmp dir,#d8 cmp @ep,#d8 cmp @ix +off,#d8 cmp ri,#d8 incw sp decw sp 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (dir) C d8 ( (ep) ) C d8 ( (ix) + off) C d8 (ri) C d8 (sp) ? (sp) + 1 (sp) ? (sp) C 1 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + + + + + + + + + + + + + + + C C C C C C C C 67 66 68 to 6f 72 74 75 77 76 78 to 7f 95 97 96 98 to 9f c1 d1 mnemonic ~ # operation tl th ah n z v c op code bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel blt rel bge rel bbc dir: b,rel bbs dir: b,rel jmp @a jmp ext callv #vct call ext xchw a,pc ret reti 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if z = 1 then pc ? pc + rel if z = 0 then pc ? pc + rel if c = 1 then pc ? pc + rel if c = 0 then pc ? pc + rel if n = 1 then pc ? pc + rel if n = 0 then pc ? pc + rel if v " n = 1 then pc ? pc + rel if v " n = 0 then pc ? pc + rei if (dir: b) = 0 then pc ? pc + rel if (dir: b) = 1 then pc ? pc + rel (pc) ? (a) (pc) ? ext vector call subroutine call (pc) ? (a),(a) ? (pc) + 1 return from subrountine return form interrupt C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + C C C + C C C C C C C C C C C C C C C C C C C C C C C C C C restore fd fc f9 f8 fb fa ff fe b0 to b7 b8 to bf e0 21 e8 to ef 31 f4 20 30 mnemonic ~ # operation tl th ah n z v c op code pushw a popw a pushw ix popw ix nop clrc setc clri seti 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r C C C s C C C C C C C C 40 50 41 51 00 81 91 80 90
41 mb89920 series n instruction map h l 0123456789abcdef 0 nop swap ret reti pushw a popw a mov a,ext movw a,ps clri seti clrb dir: 0 bbc dir: 0,rel incw a decw a jmp @a movw a,pc 1 mulu a divu a jmp addr16 call addr16 pushw ix popw ix mov ext,a movw ps,a clrc setc clrb dir: 1 bbc dir: 1,rel incw sp decw sp movw sp,a movw a,sp 2 rolc a cmp a addc a subc a xch a, t xor a and a or a mov @a,t mov a,@a clrb dir: 2 bbc dir: 2,rel incw ix decw ix movw ix,a movw a,ix 3 rorc a cmpw a addcw a subcw a xchw a, t xorw a andw a orw a movw @a,t movw a,@a clrb dir: 3 bbc dir: 3,rel incw ep decw ep movw ep,a movw a,ep 4 mov a,#d8 cmp a,#d8 addc a,#d8 subc a,#d8 xor a,#d8 and a,#d8 or a,#d8 daa das clrb dir: 4 bbc dir: 4,rel movw a,ext movw ext,a movw a,#d16 xchw a,pc 5 mov a,dir cmp a,dir addc a,dir subc a,dir mov dir,a xor a,dir and a,dir or a,dir mov dir,#d8 cmp dir,#d8 clrb dir: 5 bbc dir: 5,rel movw a,dir movw dir,a movw sp,#d16 xchw a,sp 6 mov a,@ix +d cmp a,@ix +d addc a,@ix +d subc a,@ix +d mov @ix +d,a xor a,@ix +d and a,@ix +d or a,@ix +d mov @ix +d,#d8 cmp @ix +d,#d8 clrb dir: 6 bbc dir: 6,rel movw a,@ix +d movw @ix +d,a movw ix,#d16 xchw a,ix 7 mov a,@ep cmp a,@ep addc a,@ep subc a,@ep mov @ep,a xor a,@ep and a,@ep or a,@ep mov @ep,#d8 cmp @ep,#d8 clrb dir: 7 bbc dir: 7,rel movw a,@ep movw @ep,a movw ep,#d16 xchw a,ep 8 mov a,r0 cmp a,r0 addc a,r0 subc a,r0 mov r0,a xor a,r0 and a,r0 or a,r0 mov r0,#d8 cmp r0,#d8 setb dir: 0 bbs dir: 0,rel inc r0 dec r0 callv #0 bnc rel 9 mov a,r1 cmp a,r1 addc a,r1 subc a,r1 mov r1,a xor a,r1 and a,r1 or a,r1 mov r1,#d8 cmp r1,#d8 setb dir: 1 bbs dir: 1,rel inc r1 dec r1 callv #1 bc rel a mov a,r2 cmp a,r2 addc a,r2 subc a,r2 mov r2,a xor a,r2 and a,r2 or a,r2 mov r2,#d8 cmp r2,#d8 setb dir: 2 bbs dir: 2,rel inc r2 dec r2 callv #2 bp rel b mov a,r3 cmp a,r3 addc a,r3 subc a,r3 mov r3,a xor a,r3 and a,r3 or a,r3 mov r3,#d8 cmp r3,#d8 setb dir: 3 bbs dir: 3,rel inc r3 dec r3 callv #3 bn rel c mov a,r4 cmp a,r4 addc a,r4 subc a,r4 mov r4,a xor a,r4 and a,r4 or a,r4 mov r4,#d8 cmp r4,#d8 setb dir: 4 bbs dir: 4,rel inc r4 dec r4 callv #4 bnz rel d mov a,r5 cmp a,r5 addc a,r5 subc a,r5 mov r5,a xor a,r5 and a,r5 or a,r5 mov r5,#d8 cmp r5,#d8 setb dir: 5 bbs dir: 5,rel inc r5 dec r5 callv #5 bz rel e mov a,r6 cmp a,r6 addc a,r6 subc a,r6 mov r6,a xor a,r6 and a,r6 or a,r6 mov r6,#d8 cmp r6,#d8 setb dir: 6 bbs dir: 6,rel inc r6 dec r6 callv #6 bge rel f mov a,r7 cmp a,r7 addc a,r7 subc a,r7 mov r7,a xor a,r7 and a,r7 or a,r7 mov r7,#d8 cmp r7,#d8 setb dir: 7 bbs dir: 7,rel inc r7 dec r7 callv #7 blt rel
42 mb89920 series n mask options no. part number mb89923 mb89925 mb89p928 mb89pv920 specifying procedure specify when ordering masking set with eprom programmer setting not possible 1 pull-up resistors p00 to p07, p20 to p27, p30 to p32, p90 to p97 p00 to p07, p20 to p27, p30 to p32, p90 to p97 : selectable by pin can be set per pin no pull-up resistor 2 power-on reset power-on reset provided no power-on reset selectable can be set with power-on reset 3 oscillation stabilization time slection (at 8 h z ) cystal oscillator (32.8 ms/8mh z ) ceramic oscillator (2.05 ms/8 mh z ) selectable can be set crystal oscillator (32.8 ms/8 mh z ) 4 reset pin output reset output provided no reset output selectable can be set with reset output 5 watchdog timer activation prohibited automatic activation selectable can be set inactive by default (can be activated by software) 6 low-voltage detection reset circuit activation prohibited automatic activation selectable can be set inactive by default (can be activated by software) 7 low-voltage detection reset output output disabled output enabled selectable can be set inactive by default (can be activated by software) 8 low-voltage detection voltage 3.3 v 0.3 v 3.6 v 0.3 v 4.0 v 0.3 v selectable can be set register setting 9 low-voltage detection reset/watchdog timer function selection register setting valid option setting valid selectable can be set fixed to register setting
43 mb89920 series n ordering information part number package remarks MB89923PF mb89925pf mb89p928pf 80-pin plastic qfp (fpt-80p-m06) mb89pv920cf 80-pin ceramic mqfp (mqp-80c-p01)
44 mb89920 series n package dimensions 80-pin plastic qfp (fpt-80p-m06) dimensions in mm (inches) "a" lead no. (.031.008) 0.800.20 0.30(.012) 0.25(.010) 80 65 64 41 40 25 24 1 22.300.40(.878.016) 18.40(.724)ref m 0.16(.006) (.014.004) 0.350.10 0.80(.0315)typ (.705.016) (.551.008) 14.000.20 17.900.40 20.000.20(.787.008) 23.900.40(.941.016) index 0.150.05(.006.002) (stand off) 0.05(.002)min 3.35(.132)max (.642.016) 16.300.40 ref 12.00(.472) details of "b" part 0 10 details of "a" part 0.18(.007)max 0.58(.023)max 0.10(.004) "b" 1994 fujitsu limited f80010s-3c-2 c
45 mb89920 series 80-pin ceramic mqfp (mqp-80c-p01) dimensions in mm (inches) +0.40 C0.20 +.016 C.008 +0.40 C0.20 +.016 C.008 index typ 4.50(.177) typ 6.00(.236) index area 1.50(.059)typ 1.00(.040)typ typ 1.00(.040) typ 1.50(.059) (.0315.010) 0.800.25 1.20 .047 12.00(.472)typ (.0315.010) 0.800.25 ref 18.40(.724) (.016.004) 0.400.10 1.20 .047 (.016.004) 0.400.10 max 8.70(.343) (.006.002) 0.150.05 11.68(.460)typ 9.48(.373)typ 7.62(.300)typ 0.30(.012)typ (.050.005) 1.270.13 (.713.008) 18.120.20 typ 14.22(.560) typ 12.02(.473) typ 10.16(.400) typ 24.70(.972) (.878.013) 22.300.33 (.050.005) 1.270.13 typ 0.30(.012) index area 18.70(.736)typ (.642.013) 16.300.33 (.613.008) 15.580.20 1994 fujitsu limited m80001sc-4-2 c
mb89920 series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka, nakahara-ku, kawasaki-shi, kanagawa 211-8588, japan tel: +81-44-754-3763 fax: +81-44-754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0005 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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